1. Field of the Invention
The present invention relates to a phase synchronization apparatus of Time Division Multiplexed frames (TDM frames) which synchronizes an input relative phase of TDM subframe signals with a standard relative phase.
2. Description of the Related Art
FIG. 19 shows a conventional phase synchronization apparatus of TDM frames stated in the Japanese Patent Application No. 3-60083.
In FIG. 19, a first frame counter 1b generates a position signal 14 for an input subframe address which is synchronized with an input clock signal 12 based on an input frame phase signal 13. For example, signal 13 is a pulse signal for indicating a head position of an input frame. The input subframe address is stored in the overhead of an input frame signal area (refer to FIG. 22). The input subframe address indicates each relative phase of input subframes with an input frame phase. The position signal 14 for the input subframe address is a pulse signal which indicates each position of the input subframe address.
A second frame counter 5 generates a position signal 20 for a standard subframe address which is synchronized with a standard clock signal 18 based on a standard frame phase signal 19. For example, signal 19 is a pulse signal for indicating a head position of a standard frame. The standard subframe address is stored in the overhead of a standard frame signal area (refer to FIG. 22). The standard subframe address indicates each relative phase of standard subframes with a standard frame phase. The position signal 20 for the standard subframe address is a pulse signal which indicates each position of the standard subframe address.
The first frame counter 1b generates a position signal 23a for an input subframe. The position signal 23a is a pulse signal which indicates each position of the input subframes multiplexed in the input frame. The second frame counter 5 generates a position signal 23 for a standard subframe. The position signal 23 is a pulse signal which indicates each position of the standard subframes multiplexed in the standard frame.
Depending upon the position signal 23a for the input subframe from the first frame counter 1b, a demultiplexer (DMUX) 1c demultiplexes a first to mth input subframe signal 17a (refer to FIG. 22) in a subframe signal area based on the input frame signal 11.
The input subframe address of the first to mth input subframe signal 17a is in the overhead of the input frame signal area. Depending upon the first to mth input subframe signal 17a from the DMUX 1c, a subframe type detector 2a identifies a type of subframe by a specific pattern of the input subframe address. For instance, assuming that the number of the input subframes multiplexed in the input frame is "m", then the type of the subframe is identified by "m" (m is a positive integer). The number of the subframes, that is m, is hereinafter called a "multiplexing number". The subframe type detector 2a generates a write/read control signal 16 based on the multiplexing number m=1 or m&gt;=2.
A first to nth (n&gt;=m) subframe phase synchronization means 3d, 3e, . . . , 3e are provided for synchronizing the input frame signal with the standard clock signal 18.
Depending upon the position signal 14 for the input subframe address from the first frame counter 1b, the first subframe phase synchronization means 3d controls writing data into a buffer. A data amount in the case of there being only one subframe signal in the input frame signal is hereinafter called "M". The first subframe phase synchronization means 3d generates a write address 21 to control writing data into the buffer. The write address 21 controls writing data corresponding to 1/n of the data amount M. The first subframe phase synchronization means 3d writes data corresponding to 1/n signal of the input subframe signal into the buffer when the multiplexing number from the DMUX 1c is one (m=1). The synchronization means 3d writes data corresponding to the first input subframe signal 17a into the buffer when the multiplexing number is two or more than two (m&gt;=2).
The first subframe phase synchronization means 3d controls reading data from the buffer depending upon the position signal 20 for the standard subframe address from the second frame counter 5. The synchronization means 3d generates a read address 22 which controls reading data from the buffer to correspond with 1/n of the data amount M when m=1 or 1/m of the data amount M when m&gt;=2. The synchronization means 3d reads data corresponding to 1/n signal of the input subframe signal from the buffer when the multiplexing number from the DMUX 1c is one (m=1). The synchronization means 3d reads data corresponding to the first input subframe signal 17a from the buffer when the multiplexing number is two or more than two (m&gt;=2). Thus the input relative phase is synchronized with the standard relative phase and the synchronized signal is output as a first synchronized subframe signal 17.
Each second to nth subframe phase synchronization means 3e controls writing data into the buffer depending upon the position signal 14 for the input subframe address from the first frame counter 1b and the write/read control signal 16 from the subframe type detector 2a. Each second to nth subframe phase synchronization means 3e writes data corresponding to 1/n signal of the input subframe signal into the buffer when the multiplexing number from the DMUX 1c is one (m=1). Each second to mth subframe phase synchronization means 3e writes data corresponding to the second to mth input subframe signal 17a into the buffer respectively when the multiplexing number is two or more than two (m&gt;=2).
Each second to nth subframe phase synchronization means 3e controls reading data from the buffer depending upon the position signal 20 for the standard subframe address from the second frame counter 5 and the write/read control signal 16 from the subframe type detector 2a. Each second to nth subframe phase synchronization means 3e reads data corresponding to 1/n signal of the input subframe signal from the buffer when the multiplexing number from the DMUX 1c is one (m=1). Each second to mth subframe phase synchronization means e reads data corresponding to the second to mth input subframe signal 17a respectively when the multiplexing number is two or more than two (m&gt;=2). Thus the input relative phase is synchronized with the standard relative phase and the synchronized signal is output as the second to mth synchronized subframe signal 17.
Each second to nth subframe phase synchronization means 3e selects the read address 22 from the first subframe phase synchronization means 3d when m=1 to control reading data from the buffer. Each second to mth subframe phase synchronization means 3e generates a read address 22a corresponding to 1/m of the data amount M when m&gt;=2 to control reading data from the buffer.
Depending upon the position signal 23 for the standard subframe from the second frame counter 5, a multiplexer (MUX) 4 multiplexes the first to mth synchronized subframe signal 17 from the first subframe phase synchronization means 3d and each second to nth subframe phase synchronization means 3e. The MUX 4 outputs the multiplexed signal as a synchronized frame signal 24.
A system of synchronizing the input relative phase with the standard relative phase by demultiplexing the input frame signal 11 into subframe signals is implemented in the conventional phase synchronization apparatus of TDM frames. The system is called "Phase Synchronization System With Demultiplexing Frames".
FIG. 20 shows a configuration of the first subframe synchronization means 3d.
First, depending upon the position signal 14 for the input subframe address from the first frame counter 1b, a subframe phase detector 31a detects an input subframe phase of the first input subframe signal 17a from the DMUX 1c. The detector 31a generates an input subframe phase signal (for instance, the signal is a pulse signal for indicating the head position of the input subframe).
Secondly a write controller 32 generates a write address counter enabling signal depending upon the input subframe phase signal from the subframe phase detector 31a. Depending upon the write address counter enabling signal, a write address counter 33 generates the write address 21 which controls writing into the buffer to correspond with 1/n of the data amount M when m=1 or 1/m of the data amount M when m&gt;=2. Depending upon the write address 21, a buffer memory 37a writes data corresponding to the first input subframe signal 17a from the DMUX 1c.
Thirdly a read controller 35 generates a read address counter enabling signal depending upon the position signal 20 for the standard subframe address from the second frame counter 5. Depending upon the read address counter enabling signal, a read address counter 36 generates the read address 22 which controls reading data from the buffer to correspond with 1/n of the data amount M when m=1 or 1/m of the data amount M when m&gt;=2. Depending upon the read address 22, the buffer memory 37a reads the data out as the first synchronized subframe signal 17 to the MUX 4.
At this point, an address phase comparator 34 calculates a phase difference between a phase of the write address 21 from the write address counter 33 and a phase of the read address 22 from the read address counter 36. Then when the phase difference exceeds a specific value, an error signal of phase synchronization is generated.
Depending upon the error signal, the read controller 35 turns the read address counter enabling signal "on" or "off" to shift the read address 22. Thus, the read controller 35 synchronizes the input relative phase with the standard relative phase.
FIG. 21 shows a configuration of each second to nth subframe phase synchronization means 3e. In addition to the configuration of the first subframe phase synchronization means 3d, a write selector 39 and a read selector 38 are provided in each second to nth synchronization means 3e. Depending upon the write/read control signal 16 from the subframe type detector 2a, the write selector 39 selects the write address 21 from the first subframe phase synchronization means 3d when m=1. The selector 39 selects a write address 21a from the write address counter 33 when m&gt;=2. The write address counter 33 generates the write address 21a which controls writing data into the buffer to correspond with 1/m of the data amount M.
Depending upon the write/read control signal 16 from the subframe type detector 2a, the read selector 38 selects the read address 22 from the first subframe phase synchronization means 3d when m=1. The selector 38 selects a read address 22a from the read address counter 36 when m&gt;=2. The read address counter 36 generates the read address 22a which controls reading data from the buffer to correspond with 1/m of the data amount M.
Some concrete examples are presented with FIG. 23 to FIG. 27. A frame configuration of STM-1 (STM: Synchronous Transport Module) is illustrated here. FIGS. 23 and 24 show the frame configuration of STM-1. FIG. 23 shows the frame configuration in the case of the multiplexing number being one (m=1). FIG. 24 shows the frame configuration in the case of the multiplexing number being three (m=3).
The size of a frame of STM-1 is 270 bytes by 9 rows. An overhead and a payload are stored in one frame. In the overhead, a section overhead (SOH: all the part of the overhead except the fourth row) and a pointer (PTR: the fourth row of the overhead) are stored. SOH is used for synchronizing frames and watching errors. The first 6 bytes of SOH are used for synchronizing frames. The pointer is placed at the fourth row in the figure. The pointer contains some values (addresses) each of which means a phase difference between a head position of the input frame signal and each head position of the multiplexed subframe signals.
Various kinds of virtual containers (VC) are placed in the payload. FIG. 23 relates to a synchronous transport module level 1 (64 Kb/S for 2016CH) STM-1 (156 Mb/s) frame configuration. FIG. 23 shows the case of there being only one virtual container in the payload, in other words it shows the case of the multiplexing number being one (m=1). Bytes H11 and H21 are used as a pointer when the multiplexing number is one. An address of the head position of a multiplexed signal of a virtual container in the payload is shown by using the two bytes H11 and H21. Therefore, when the head of the virtual container is data k1, H11 and H21 show an address wherein the data k1 is stored. Bytes H12 and H22 are used as a second pointer when another virtual container in addition to the above one is placed in the payload. Bytes H13 and H23 are used as a third pointer when there is yet another virtual container in the payload. Since FIG. 23 shows the case of the multiplexing number being one, only one virtual container is multiplexed in it. Therefore pointers H12, H13, H22 and H23 show a fixed value.
The case of the multiplexing number being three is now presented with FIG. 24. FIG. 24 relates to STM-1: synchronous transport module level 1 (64 Kb/S for 2016); VC-32: virtual container 32 (64 K/S for 672 CH); VC-11: virtual container 11 (64 Kb/s for 24 CH) and STM-1 (156 Mb/s) frame configuration. Since the multiplexing number is three, there are three virtual containers in the payload. Assuming that data a1 is a head data of the first virtual container (VC#1) which is multiplexed first, the address of the data a1 of the first virtual container (VC#1) is stored by using the two bytes H11 and H21. Assuming that data a2 is the head data of the second virtual container (VC#2) which is multiplexed secondly, the address of the data a2 of the second virtual container (VC#2) is stored by the two bytes H12 and H22. Assuming that data a3 is the head data of the third virtual container (VC#3) which is multiplexed thirdly, the address of the data a3 of the third virtual container (VC#3) is stored by the two bytes H13 and H23.
A timing chart of some signals shown in FIG. 19 is presented with FIG. 25. When the input frame signal 11 is input, the input frame phase signal 13 is turned on synchronous with the input clock signal 12 at the head byte of the signal 11. At the moment when the address indicating the head position of the multiplexed subframe signal, that is, the pointer (the fourth row in the overhead) of the input frame signal 11 is input, the position signal 14 for the input subframe address is output from the first frame counter 1b. Since the input frame phase signal 13 is input in the first frame counter 1b, at the moment when 270 bytes by 3 rows have passed since the input, that is, at the head byte of the fourth row, the first frame counter 1b turns on the position signal for the input subframe address. In other words, at the time of the byte H11, a position signal 14-1 for the input subframe address shown in FIG. 25 is turned on. At the time of the byte H12, the first frame counter 1b turns on a position signal 14-2 for the input subframe address. At the time of the byte H13, a position signal 14-3 is turned on. Similarly, at the time of bytes H21, H22, H23, position signals 14-1, 14-2, 14-3 for the input subframe address are turned on in turn respectively. The position signals 14-1, 14-2, 14-3 are input into the first, the second and the third subframe phase synchronization means respectively. The subframe phase synchronization means detects the address of the head position of the subframe depending upon the moment of the inputted position signal for the input subframe address. Then, using the address of the head position of the subframe, the synchronization means stores the data that follows the head position into the buffer memory.
FIG. 26 illustrates an operation of the DMUX 1c and the MUX 4 shown in FIG. 19. FIG. 26 shows the case of the multiplexing number being one. Data k1, k2, k3, . . . is supposed to be contained in the input frame signal. The buffer memory is supposed to be empty, that is to have no data in it. The DMUX 1c inputs the input frame signal 11 and outputs the first, the second and the third subframe signal. For instance, each data of k1, k2, k3 is separated into the first, the second, the third subframe signal respectively by the DMUX. While the DMUX 1c outputs signals of data k1, k2, k3 respectively as a subframe signal, "1" is generated as the write address of the buffer memory. Accordingly data k1, k2, k3 are stored in the address "1" of each buffer memory. Similarly, data k4, k5, k6 being input after k1, k2, k3 are separated into the first, the second and the third subframe signal by the DMUX 1c. While each data k4, k5, k6 are output as the subframe signal, "2" is generated as the write address of the buffer memory. Accordingly data k4, k5, k6 are stored in the address "2" of each buffer memory. All these operations are done being synchronized with input clock signal 12.
Depending upon the standard clock signal 18, data stored in the buffer memory is read out by the MUX 4. In the case of "1" being generated as a read address, the buffer memory outputs data k1, k2, k3 in the address "1". While the read address outputs "1", the buffer memory keeps outputting data k1, k2 ,k3 respectively as the first, the second, the third synchronized subframe signal. Depending upon the standard clock signal, the MUX 4 generates a synchronized frame signal based on the output synchronized subframe signal.
FIG. 27 illustrates an operation of the DMUX and the MUX in the case of the multiplexing number being three. The operations presented in FIG. 26 almost correspond to the operation in the case of the multiplexing number being three. The operation shown in FIG. 27 differs from the operation shown in FIG. 26 in that each data of the input frame signal and the synchronized frame signal is byte interleaved per data stored in the virtual container. In other respects, FIG. 27 corresponds to FIG. 26.
Besides, there is a conventional circuit or apparatus for lining up heads of subframes multiplexed in a multiplexed frame signal. It is called a frame aligner here.
FIG. 28 shows the conventional frame aligner disclosed in the Unexamined Japanese Patent Publication No. 4-2233. The frame aligner can synchronize the phase of the frame of each highway signal multiplexed in an input highway multiplexed signal D11 by time sharing.
This circuit for frame phase synchronization has a circuit 111 for detecting a frame head, which detects a time of an input frame head at each digital line. The circuit also has a first frame counter 113. The frame counter 113 calculates an input frame phase and generates the input frame phase signal at each digital line depending upon the time of the input frame head detected by the circuit 111.
In addition, the circuit has a second frame counter 118. The frame counter 118 calculates a common frame phase for synchronizing a frame phase of each digital line with a common phase, and generates a common frame phase signal.
The circuit for frame phase synchronization has a frame memory 116. The frame memory 116 stores data on frames at each digital line temporarily, using the input frame phase signal generated by the first frame counter as a write address. And the frame memory 116 outputs each digital line with a common phase, using a common frame phase signal generated by the second frame counter as a read address.
The circuit also has a circuit 119 for phase comparing and controlling. The circuit 119 compares the input frame phase signal of the first frame counter and the common frame phase signal of the second frame counter at the each digital line. Then, the circuit 119 revises the phase of the first frame counter when the input frame phase and the common frame phase indicate close correspondence.
As described above, the circuit for frame phase synchronization comprises a logical processing circuit and a memory. The logical processing circuit comprises the circuit 111 for detecting the frame head, the first frame counter 113 and the circuit 119 for phase comparing and controlling respectively in time sharing per each line in order depending upon a multiplexing order of the digital line. The memory stores a result of processing by the logical processing circuit temporarily. The frame phase synchronization circuit synchronizes frame phases in time sharing.
For the purpose of making a configuration of the frame aligner simple and small, the aligner is supposed to be able to synchronize the frame phases of the multiplexed highway signals in the intact multiplexing condition. In other words, each highway signal (each digital line) is synchronized by a time sharing process.
Thus all highway signals read out from the frame memory 116 have a unified phase. The multiplexed highway signal is output as a signal D12. Namely, the signal D12 output from the frame memory 116 has already become a highway multiplexed signal wherein the head positions of all highway signals are aligned. By the configuration stated above, a unified synchronization for frame phase can be accomplished at each highway.
FIG. 29 shows a circuit of a conventional multiplexed frame aligner disclosed in the Unexamined Japanese Patent Publication No. 1-228228.
The circuit of multiplexed frame aligner makes different frame phases of multiplexed channel data suited for a specific standard phase.
The circuit has a detector 201 for a multiplexed synchronization. The detector 201 inputs the multiplexed channel data, detects synchronization of frames by checking the multiplexed channel data, and outputs a frame pulse corresponding to a specific common data position in each channel data.
The circuit has a detector 202 for detecting a multiplexed phase difference. The detector 202 detects a phase difference between the standard phase and each frame pulse for each channel.
The circuit has a delay generator 203 which generates a delay corresponding to the phase difference at each channel.
The circuit has an output controller 204 which delays each channel data corresponding to an amount of delay.
The circuit has a channel address generator 205 which gives each address to each circuit stated above. The address corresponds to each channel.
The circuit of multiplexed frame aligner detects synchronization of frames from multiplexed input data in the detector 201 for the multiplexed synchronization. And the detector 201 outputs a frame pulse, for each channel, corresponding to a specific common data position in the frame, depending upon each channel address from the channel address generator 205. The frame pulse is compared with a standard phase signal at the detector 202 for the multiplexed phase difference. The phase difference between the standard phase and the frame pulse is detected for each channel. The detected phase difference for each channel is sent to the delay generator 203. An amount of delay corresponding to the phase difference is generated in the generator 203. The generated delay amount of each channel is sent to the output controller 204 and delays data of each channel depending on the amount of delay. Therefore the data suited for the standard phase can be always output.
As mentioned above, the conventional frame aligner is shown in FIGS. 28 and 29.
The circuit for frame phase synchronization shown in FIG. 28 aligns a phase of each highway signal with the standard frame phase by inputting the highway multiplexed signal without demultiplexing, writing data into the frame memory in time sharing, reading it using the unified phase. The object of the circuit is to align heads of subframes multiplexed in the multiplexed frame signal. Since the circuit is supposed to align head positions of highway signals in the output highway multiplexed signals, it doesn't have means for controlling reading data from the frame memory. Since the circuit is supposed to align head positions of highway signals, the frame memory needs enough area to store a respective highway signal and information on frames.
The circuit of multiplexed frame aligner shown in FIG. 29 aligns a head of each channel data with the standard frame phase by detecting the phase difference between the phase of channel data multiplexed in the multiplexed frame signal and a standard phase, putting a delay corresponding to the phase difference at each channel.
The multiplexed frame aligner described above aligns heads of subframes multiplexed in the multiplexed frame signal.
As stated above, the frame aligner is supposed to align heads of subframes multiplexed in the multiplexed frame signal.
The object of the present invention is to improve a frame phase synchronization apparatus which inputs the input frame signal being synchronized with the input clock signal and outputs the synchronized frame signal synchronous with the standard clock signal, so as to synchronize data, which is synchronized with the input clock signal, with the standard clock signal.